1. Field of the Invention
The present disclosure relates generally to reduced power consumption, and more specifically to a low leakage CMOS cell with low voltage swing for reduced power consumption and having a reduced footprint.
2. Description of the Related Art
As integrated circuit (IC) design and fabrication techniques continue to advance, operating voltages and device sizes have each scaled downward. Complementary Metal-Oxide Semiconductor (CMOS) circuitry dissipates less power and is more dense than other types of integrated circuit (IC) technologies so that CMOS technology has become the dominant style of digital circuit design for integrated circuits. CMOS circuits typically use a combination of N-channel (NMOS) and P-channel (PMOS) devices (e.g., transistors) each having a threshold gate-to-source voltage based on design, scale, materials and process. As device sizes and voltage levels have decreased, the channel lengths and oxide thicknesses of each device have also decreased. Sub-threshold leakage current is the current that flows between the drain and source when the gate-to-source voltage is below the threshold voltage of the CMOS device. In such conventional configurations the sub-threshold leakage current may account for a significant amount of total power consumption of the IC especially at higher temperatures. Leakage current may consume a significant amount of power even when the IC is otherwise idle.
Many IC designs incorporate a significant number of CMOS cells (e.g., configured as buffers, inverters, gating devices, flip-flops, etc.) for performing a variety of functions, including a few non-limiting examples such as signal distribution, signal processing, maintaining digital signal integrity, etc. As used herein, the term “cell” is defined as any CMOS circuit incorporating any combination of PMOS and NMOS transistors for performing any suitable function, such as buffers, inverters, flip-flops, etc. Clock distribution involves a significant portion of the total circuitry and total number of transistors. Reducing the power consumption of the clock distribution network, therefore, is advantageous in reducing overall power. Buffer cells are often used for clock signal distribution within one or more clock trees. Low-swing clock tree design is a method used to reduce power in the clock tree. One method to achieve low-swing is to use a single lower voltage level in the IC design. In this method, a combination of transistors and/or other circuitry is used to shift the output swing to a lower voltage level due to inherent threshold voltage of the transistors. This method tends to substantially increase overhead cost in terms of additional design effort and increased area consumption.
Another method to achieve low-swing of signals, including clock signals, is to create a separate lower voltage level. The conventional approach to this method is to provide transistors operating in a lower voltage domain. The transistors operating in the lower voltage domain must be separated, however, from those operating in the higher voltage domain using well isolation. Well isolation means separating the semiconductor wells of low voltage cells from those of higher voltage cells by a sufficient isolation distance. During chip design, such well isolation creates issues in terms of well continuity and placement of well ties for the different voltage domains. Such well isolation, for example, consumes valuable area of the IC to isolate the different voltage domains. Layout design effort is substantially increased in an attempt to ensure proper isolation between the separate voltage domains while minimizing the area consumption of isolation barriers.